1. Field of the Invention
The present invention relates to a semiconductor device consolidating a logic circuit and a static memory (SRAM) circuit.
2. Description of the Related Art
Japanese Published Unexamined Patent Application No. Hei 7-86916 discloses a construction in which a logic circuit is provided with a power switch and a MOS transistor constructing the logic circuit is back-gate biased. Japanese Published Unexamined Patent Application No. 2000-207884 discloses a substrate bias control technology for a system LSI operable at a low voltage including a static memory. Japanese Published Unexamined Patent Application No. 2001-93275 discloses a construction in which a logic circuit is provided with a logic power source and a memory circuit is provided with a memory power source.
Currently, semiconductor integrated circuits called a system LSI (Large Scale Integrated Circuit) integrating an SRAM circuit and a logic circuit on the same semiconductor chip are widely manufactured. The SRAM circuit refers to a circuit functioning as a memory by only the circuit including arrayed SRAM memory cells and a peripheral circuit for accessing the memory cells. The logic circuit refers to a circuit subjecting an inputted signal to a specified process for output, other than the memory circuit including arrayed memory cells such as an SRAM, a dynamic memory (DRAM) and a non-volatile memory and a circuit for accessing the memory cells. A circuit holding data such as a flip-flop in the logic circuit is thought to be part of the logic circuit.
A request for low power consumption of the system LSI and finer transistors in the LSI lower the source voltage of the LSI. In a 0.13 xcexcm process, a LSI operated at a source voltage of 1.2V is manufactured. When the source voltage is lowered, the electric current of the MOS transistor is reduced to deteriorate the circuit performance. To prevent the performance from being deteriorated, a LSI lowering the threshold voltage of the MOS transistor is manufactured.
When the threshold value of the MOS transistor is lowered, a leakage current called a sub-threshold current of the MOS transistor is increased. The leakage current continues to flow at the time of operation or non-operation of the circuit. In the standby state, the SRAM does not perform write and read operations, but continues to hold data. The power consumption in the standby state of the system LSI is the leakage current of the MOS transistor in the circuit. When the threshold voltage of the MOS transistor is lowered, the power consumption in the standby state is increased. In the system LSI, the state that the logic circuit is not operated and the SRAM circuit holds data is called a standby state.
The logic circuit is not operated at the time of standby. The logic circuit cuts off the power source using a switch to reduce the leakage current. The SRAM memory cell is of a flip-flop construction. The leak current is relatively small. In the prior art system LSI, the capacitance of the SRAM circuit mounted is not large and the SRAM memory cell is made by the MOS transistor having a high threshold value. The leakage current in the SRAM circuit has not been a problem. However, when the MOS transistor is made finer and a large-capacitance SRAM is mounted on the system LSI so as to lower the threshold voltage of the MOS transistor constructing the SRAM memory cell, the leakage current in the SRAM memory cell cannot be ignored. The logic circuit can reduce the leakage current at the time of standby when the power source is cut off by the switch. The SRAM circuit must hold data in the standby state. The power source cannot be cut off so that the leakage current cannot be reduced. When the voltage is lowered to reduce the threshold voltage of the MOS transistor, the leakage current in the circuit attached for accessing the memory cell in the SRAM circuit is increased.
The summary of the representative inventions disclosed in this application will be described as follows.
(1) In a LSI consolidating a logic circuit and an SRAM circuit, the power source of the logic circuit is cut off by the switch at the time of standby, and the SRAM circuit controls the substrate voltage of the MOS transistor so as to reduce the leakage current.
(2) The power source of the control circuit for accessing the memory cell in the SRAM circuit is divided to be cut off, reducing the power consumption.
(3) The SRAM circuit is divided so that some SRAMs hold data at the time of standby and other SRAMs not holding data cut off the power source to reduce the leakage current.